Abstract
Researchers at the University of Central Florida have developed four inventions to enhance netlist analysis. A netlist is a description of the connectivity of an electronic circuit. Together, the tools can help to detect code flaws and malicious logic in integrated circuits (ICs) and assure IC integrity and accessibility. They can also enable exports of netlists for use by other analysis tools and provide graphical views of a netlist. Following are brief descriptions of the inventions:
- RERTL, the UCF Register Transfer Level (RTL) code recovery tool: RTL code is specialized computer language used to describe the structure and behavior of electronic circuits. UCF’s RERTL leverages advanced graph algorithms to assist in netlist analysis. Typically, design defects (due to the influence of complex third-party IP designs with shorter time-to-market constraints or even malicious code) may be found and corrected with knowledge of RTL. Yet, these flaws may not be detected if third-party IP designs do not use or allow access to the RTL source code. Supported by RERTL, these logical states and their interactions are recovered and converted into human-readable RTL.
- Netlist Assessment Toolset (NETA): A software toolset, NETA aids IP users in assuring the confidentiality, integrity, and accessibility of their Integrated Circuit (IC) or third-party IP core. Ensuring the quality and trustworthiness of third-party resources has been a hard problem to tackle. Researchers have shown that analyzing ICs without golden models is challenging. The discussed toolset gives access to a slew of gate-level analysis tools, many of which are heuristic-based for extracting high-level circuit design information.
- NetA Verilog Exporter for Yosys: The UCF plugin is for the open-source Yosys netlist synthesis tool that exports netlists in a form usable by NETA, a suite of netlist analysis tools created by UCF and the University of Florida.
- NetViz: A graphical interface (GUI) for hardware security work, NetViz allows users to run multiple existing tools (the NETA toolset) with a graphical view of the netlist and the tool results. It also chains the tools together in a helpful way.
Benefit
Supports the use of netlists in integrated circuit designs and development processesMarket Application
Hardware security analysis