Research Terms
Warren B. Nelms Institute for the Connected World (The Nelms Institute)
| Director |
Swarup Bhunia |
| Phone | (352) 392-5989 |
| Website | https://iot.institute.ufl.edu/ |
| Mission | The Warren B. Nelms Institute for the Connected World was established to lead research and education in all aspects of the intelligent connection of things, processes, people, and data that address major world challenges including health, energy, transportation, and manufacturing. Together with industry, university, and government partners, the Nelms Institute will develop broad, interdisciplinary Internet-of-Things (IoT) technologies, applications, and policies to create more secure and connected communities. To fuel the next industrial revolution, the Institute will promote tech transfer, entrepreneurship, policy, education and outreach in IoT and its integral components of sensors, low-power embedded processing, communication, networking, cloud computing, data analytics, machine learning, security, privacy and trust. |
This computer system memory architecture employs human brain-inspired algorithms that intelligently optimize data storage, retrieval, and maintenance. Worldwide spending on data storage units is expected to exceed $78 billion by 2021. Conventional computer memory architectures can be problematic for applications that store copious amounts of data. Most stored data is often useless and irrelevant, such as the hours of inactivity in a security camera footage. With growing expenditures on data storage, many companies need a better system to optimize computer memory space.
Researchers at the University of Florida have developed a computer memory framework that uses artificial intelligence to process data and optimize storage. The memory framework mimics functions of the human brain when storing information, potentially saving computer storage space and enhancing memory efficiency.
Computer memory system using algorithms based on human brain processes that intelligently execute data operations to improve memory performance for various electronic computing systems
The computer system memory framework emulates many fundamental processes of human memory. The configuration of the memory architecture enables intelligent decisions via statistical reinforcement learning and the use of frequency-weighted averages. Based on memory access/storage patterns, the artificial intelligence framework learns to optimize the memory for increased storage and retrieval efficiency. It learns using memory operation algorithms that optimize how the computer system adds, moves, and modifies data units, improving overall memory performance.
This physical unclonable function (PUF) based authentication and key generation mechanism utilizes the existing reconfigurable logic elements of an FPGA (Field-Programmable Gate Array) to enhance a device's security. An FPGA facilitates reconfiguring a device’s functionality by reprogramming its logic elements, even after deployment. This feature makes them an attractive and cost-effective option for diverse applications. The global FPGA market should reach $8.6 billion by 2025. The use of FPGAs in applications demanding high levels of security – for instance, an F-35 fighter jet – propels the need for robust hardware security measures. The existing PUF-based security solutions mostly rely on external components, and as they are exposed to adversaries, it makes the FPGAs vulnerable to potential attacks. They also occupy more system resources (e.g., logic elements) and are expensive to implement.
Researchers at the University of Florida have developed a synthesizable physical unclonable function-based authentication technique that generates device-specific digital signatures. This security measure is conservative on system resources, utilizes the existing on-board infrastructure, and can be realized at a negligible cost.
Create a synthesizable physical unclonable function in an FPGA as a security measure
To provide programmable security on an FPGA, UF researchers suggest a solution they term MeL PUF, meaning Memory-in-Logic PUF. It exploits the existing reconfigurable logic elements on an FPGA as an intrinsic source of randomness(entropy. This technique transforms the inherent randomness into a unique key that serves as a device-specific, unique digital fingerprint.
This autonomous system charges networked, battery-operated electric vehicles while they are in motion and reduces the need for central charging stations. Transportation solutions that rely on mobile battery power are on the rise; increasing demand for fuel-efficient, high-performance, and low-emission transportation will lead to electric vehicles accounting for 18 percent of new automotive sales in the U.S. by 2028 . Despite this demand, the charging infrastructure for battery-powered vehicles remains inefficient, relying on a limited number of stations that operate on a first-come, first-served basis. Additionally, the vehicles must remain at these fixed stations for an extended time during the charging process, hindering electric vehicle adoption due to user inconvenience.
Researchers at the University of Florida have developed a system for efficiently charging cloud-linked electric vehicles without requiring them to stop. The system creates a network of electric cars, drones, robots, etc., each able to exchange charge with all other vehicles registered to the network. This facilitates efficient charge distribution and convenient, on-the-go charging.
Power management system that charges the batteries of electric vehicles while moving and increases efficiency of large-scale electric vehicle networks
An autonomous system generates a charge distribution map from real-time information transmitted by vehicles registered to the cloud-based charging network. These vehicles may be at various charge stations and may join charging networks as requested. The system runs a scheduling algorithm in the cloud using the charge distribution map data and other network information to coordinate charge transfers from one vehicle to another. These exchanges can redistribute network charges based on the demand of individual electric vehicles, allowing each vehicle to function at optimum working level according to the total amount of available charge stored in the network.
This virtual architecture interface improves both security and performance for field-programmable gate arrays (FPGAs). FPGAs are integrated circuits that can be configured — and reconfigured — by a customer after manufacture. They function almost as blank slates, which the customer can customize with a bit file. This flexibility allows FGPA use in a wide variety of fields, including wearable electronics, space exploration, defense and the internet of things (IoT), which refers to the connection of devices like appliances, cars or health monitors to the internet. Available computer-aided design (CAD) tools for FPGAs fail to provide the security, performance, and programmability that these types of uses demand.
Researchers at the University of Florida have developed a full bridge LLC resonant converter that automatically dampens the amount of electromagnetic interference produced.
These virtual architecture interfaces provide a range of overlay architectures to improve the performance, security, and programmability of FGPAs
Unique virtual architectures make the underlying hardware appear different on every FPGA device, despite having the same functionality, by separating true device functionality from hardware-specific resources. The architecture interface makes reverse engineering, piracy, and tampering difficult because while the actual FPGA architecture is described in documentation, and the hardware itself is identical among specific devices. The overlay architecture can be proprietary for a company or product and kept confidential. The automatically-generated architectural variants can deter large-scale piracy and reverse engineering efforts.
This drone-based administration framework services and assists Internet of Things remote devices using unmanned aerial vehicles. The advent of the Internet of Things (IoT) has enabled the deployment of many low-cost remote devices for automating various tasks in day-to-day life. These devices are battery-operated, making them portable and easy to place virtually anywhere. However, the remote nature of these devices makes their maintenance an arduous task. In addition, routine maintenance tasks, such as replacing batteries, data back-up, and debugging, are performed by humans. Having human workers service the remote devices poses an occupational and environmental hazard, particularly with the devices geographically spread over a wide area.
Researchers at the University of Florida have developed DARLING: Drone-Based Administration of Remotely Located Instruments and Gears, a drone-based administration framework for the servicing of remote devices. Through the use of unmanned aerial vehicles (UAV), DARLING provides remote Internet of Things (IoT) devices with required maintenance operations, such as battery replacement, data back-up, and more. This automates the maintenance of hard-to-access remote IoT devices in place of on-site human workers.
Drone-based administration framework for servicing remote Internet of Things (IoT) devices, optimizing and anticipating maintenance, and removing the occupational and environmental hazards posed to workers
The DARLING architecture consists of three hardware components: the unmanned aerial vehicle (UAV), a base station responsible for housing the UAV, and the target remote device serviced by the UAV. The base station makes the high-level decisions in determining appropriate maintenance tasks for the UAVs to perform on certain devices in an appropriate time frame. It provides the UAV with information about the remote device and its general vicinity. The UAV uses this information to self-navigate to the device’s general location. Using either firsthand knowledge about the device’s environment or gathering information via its camera and direct communication with the device, the UAV determines the proper maintenance configuration. The UAV is capable of landing near the remote device to transfer batteries and data between itself and the remote device. Once maintenance is complete, the UAV will continue to service other devices and return to the base station after all of them to charge its own batteries and transfer data to the secure storage. DARLING is capable of routine, reactive, and predictive maintenance. Routine maintenance is schedule-based, while reactive and predictive maintenance is based on AI models.
This protective framework prevents piracy and theft of the intellectual property of electronic devices. Intellectual property theft is a prominent issue in the electronic hardware industry. U.S. firms estimate that over $1.3 billion is lost annually from foreign patent infringements. Electronic hardware is subject to intellectual property threats, such as the cloning of design features and the sale of excess manufactured chips under different names.
Researchers at the University of Florida have developed integrated circuit chips that protect hardware from intellectual property theft. The protection uses disappearing “vias” (the interconnections in electronic devices) within the integrated circuit to disguise the design of the hardware. These vanishing vias are impossible to locate without the necessary encryption keys, effectively disguising the structure of the circuits and protecting the hardware from intellectual property theft.
Circuit design for electronic devices to protect against reverse engineering, intellectual property theft, and hardware Trojan insertion
This hardware design applies vanishing vias to integrated circuit chips and printed circuit boards (PCB) to protect electronic devices from reverse engineering, such as cloning, IP infringement, or hardware Trojan insertion. Vias are informational pathways vital in the functioning of multi-layered circuits. This framework requires a configuration key to correctly set the vias' statuses and enable the device's functions. Once the desired operation is finished, the vias will be set as disconnected, making the interconnection "vanished," thereby concealing the chip’s logic function. Furthermore, dummy vias can provide additional obfuscation so that it is extremely difficult, if even possible, for an IP thief to understand the device's structure. These protective methods prevent criminals from identifying key components of the chips, thus preventing their ability to reverse engineer the chip’s functions and sell the technology as their own.
These nano-electromechanical systems (NEMS) barcodes use nano-sized arrays to create microscopic, non-cloneable labels and IDs with unprecedented immunity to counterfeiting. Businesses and other institutions rely on barcodes and other identifiers (i.e. radiofrequency IDs) to monitor and track their inventory for authenticity verification, supply chain management, and automated purchasing and check-out of products. Barcodes dominate the field of automatic identification and data capture (AIDC) because they are easy to use, effective and cheap. However, available barcode systems are vulnerable to counterfeiting and other forms of exploitation, which is particularly problematic when tracking valuable or sensitive items, such as electronics or prescription painkillers. Researchers at the University of Florida have developed a nano-electromechanical systems barcode generator that layers or engraves tiny barcodes directly onto a substrate or product, such as mechanical parts, plastic and glass packaging, food and medicine, and medical devices. The microscopic size lends itself to clandestine barcodes and the layering process includes a protective layer; both attributes make the barcodes highly immune to cloning or tampering. In addition, mechanical removal and reapplication of the barcode results in irreversible physical damage.
Non-cloneable, nano-sized barcode generation for AIDC
The barcode, fingerprint, labeling or watermark device comprises a substrate, a microscopic array of identification dots engraved on a substrate, plus other layers that may include an interdigital transducer, a piezoelectric layer, and passivation or protective layers. The interaction of acoustic waves within the nanostructure dots generates distinct resonance modes that stand out in the frequency response. The pattern generated by each nanostructure represents a spectral signature, which can be detected and identified by a receiving device. Because of the nature of the nanostructure, it cannot be removed from the substrate without irreparable physical damage, unlike a traditional barcode. In addition, the barcode can be clandestine due to its nano-size. Furthermore, the materials used in the barcode are bio-degradable, meaning it can be safely used for biomedical applications.
This hardware security training platform uses various hardware components integrated onto a printed circuit board (PCB) to facilitate targeted experiments, developing a user’s skill in hardware security. As technological devices become more complex and interconnected, the demand for mechanisms to validate and protect cyber and hardware systems has increased, resulting in the emergence of hardware security engineering. Security engineers examine various device exposures and design methods to minimize susceptibility to foreign invasion and tampering, such as buffer overflow or Trojan attacks. To better prepare next-generation hardware security engineers, universities, engineering firms, and technical vocational schools provide rigorous training through modules involving hacking experiments focused on concepts such as logic design, lower-level programming, or encryption/decryption algorithms. However, available hardware security training platforms do not provide those preparing for technical internships or professions with comprehensive and hands-on experience defending hardware systems from hacks or cyberattacks.
Researchers at the University of Florida have developed an integrated PCB training platform that combines over twenty crucial hardware security experiments to better prepare technical students to defend against cybersecurity threats. Through the various computing hardware components and compatible software packages, users conduct hands-on experiments in the field of hardware security and gain experience protecting hardware systems from cyberattacks.
Integrated training and experimentation platform for better preparing computer engineering students and employees at technical universities or firms to protect hardware systems from various cybersecurity breaches
This training platform includes numerous electrical components that students employ as they conduct various hardware security experiments. Among the components includes an Atmel microcontroller, an FPGA chip, LEDs, switches, Bluetooth sensors, and others which are all soldered onto a single printed circuit board (PCB). Using this PCB and accompanying experiment modules, students perform various hardware engineering tasks that will prepare them for real-world threats to cybersecurity. For instance, the FPGA and external EEPROM train students to design large logical circuits that detect potential foreign attacks.
