-
"Experience of Administering Our First S-STEM Program to Broaden Participation in Computer Science"
2020 ▪
-
"Amniote: A User Space Interface to the Android Runtime"
2019 ▪
-
"Agave: A benchmark suite for exploring the complexities of the Android software stack"
2016 ▪
G. Tyson;
Sally A. McKee;
Zachary Yannes;
Martin K. Brown;
Michael Lustig;
Mazdak Sanati;
Steven K. Reinhardt;
-
"Interactive Augmented Reality for Dance."
2016 ▪
ICCC
G. Tyson;
Taylor Brockhoeft;
Jennifer Petuch;
James Bach;
Emil Djerekarov;
Margareta Ackerman;
-
"An Examination of Dynamic Gene Expression Changes in the Mouse Brain During Pregnancy and the Postpartum Period"
2015 ▪
G3 Genes Genomes Genetics
-
"Scheduling instruction effects for a statically pipelined processor"
2015 ▪
Compilers, Architecture, and Synthesis for Embedded Systems
-
"Serious 3D gaming research for the vision impaired"
2015 ▪
G. Tyson;
Justin B Marshall;
Juan Llanos;
Roberto Miguel Sanchez;
Francisca B. Marshall;
-
"DNA-Encoded Chromatin Structural Intron Boundary Signals Identify Conserved Genes with Common Function"
2015 ▪
International Journal of Genomics
-
"A journey toward obtaining our first NSF S-STEM (scholarship) grant"
2014 ▪
-
"Improving processor efficiency by statically pipelining instructions"
2013 ▪
-
"Improving processor efficiency by statically pipelining instructions"
2013 ▪
-
"Improving processor efficiency by statically pipelining instructions"
2013 ▪
ACM SIGPLAN Notices
-
"PROGRAM DIFFERENTIATION"
2012 ▪
Journal of Circuits Systems and Computers
-
"Creation and modification of models of nucleosome occupancy and their applications across multiple species"
2012 ▪
-
"There and back again...a datum's tale"
2012 ▪
-
"An Overview of Static Pipelining"
2011 ▪
IEEE Computer Architecture Letters
-
"ContextProvider: Context awareness for medical monitoring applications"
2011 ▪
G. Tyson;
M. Mitchell;
C. Meyers;
A-I A. Wang;
-
"Improving Low Power Processor Efficiency with Static Pipelining"
2011 ▪
-
"BEAT: Bio-Environmental Android Tracking"
2011 ▪
-
"A computational exploration of gene regulation by nucleosome position"
2010 ▪
-
"Effect of sequences on the shape of protein energy landscapes"
2010 ▪
-
"iWander: An Android application for dementia patients"
2010 ▪
-
"CRC: Protected LRU Algorithm"
2010 ▪
-
"Program differentiation"
2010 ▪
-
"Characterizing Energy Landscapes of Proteins and Identifying Shape-Determining Factors"
2010 ▪
Biophysical Journal
-
"iFall: An android application for fall monitoring and response"
2009 ▪
-
"Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)"
2009 ▪
ACM SIGPLAN Notices
-
"Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE)"
2009 ▪
-
"Core monitors"
2009 ▪
G. Tyson;
Sally A. McKee;
Paul E. West;
Yuval Peress;
-
"Practical exhaustive optimization phase order exploration and evaluation"
2009 ▪
ACM Transactions on Architecture and Code Optimization
-
"FRESS: an Efficient Monte Carlo Method for Biopolymer Structure Simulation"
2009 ▪
Biophysical Journal
-
"Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education"
2009 ▪
Springer eBooks
-
"Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems"
2009 ▪
Lecture notes in computer science
G. Tyson;
Sally A. McKee;
Major Bhadauria;
Karan Singh;
-
"Enhancing the effectiveness of utilizing an instruction register file"
2008 ▪
Proceedings - IEEE International Parallel and Distributed Processing Symposium
-
"An Interactive Compiler Development System"
2008 ▪
-
"Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache"
2007 ▪
Proceedings of the ... annual International Symposium on Microarchitecture/Proceedings of the annual International Symposium on Microarchitecture
-
"Facilitating compiler optimizations through the dynamic mapping of alternate register structures"
2007 ▪
-
"Addressing instruction fetch bottlenecks by using an instruction register file"
2007 ▪
ACM SIGPLAN Notices
-
"Addressing instruction fetch bottlenecks by using an instruction register file"
2007 ▪
-
"Evaluating Heuristic Optimization Phase Order Search Algorithms"
2007 ▪
-
"Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache"
2007 ▪
-
"Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems"
2007 ▪
Lecture notes in computer science
G. Tyson;
Sally A. McKee;
Major Bhadauria;
Karan Singh;
-
"Specializing Cache Structures for High Performance and Energy Conservation in Embedded Systems"
2007 ▪
Lecture notes in computer science
-
"Adapting compilation techniques to enhance the packing of instructions into registers"
2006 ▪
-
"Reducing Instruction Fetch Cost by Packing Instructions into RegisterWindows"
2006 ▪
-
"In search of near-optimal optimization phase orderings"
2006 ▪
ACM SIGPLAN Notices
-
"In search of near-optimal optimization phase orderings"
2006 ▪
-
"Reducing the cost of conditional transfers of control by using comparison specifications"
2006 ▪
ACM SIGPLAN Notices
-
"Reducing the cost of conditional transfers of control by using comparison specifications"
2006 ▪
-
"Exhaustive Optimization Phase Order Space Exploration"
2006 ▪
-
"High-quality ISA synthesis for low-power cache designs in embedded microprocessors"
2006 ▪
IBM Journal of Research and Development
-
"Application-specific architecture framework for high-performance low -power embedded computing."
2006 ▪
Deep Blue (University of Michigan)
-
"Improving performance and energy consumption in region-based caching architectures"
2006 ▪
G. Tyson;
Trevor N. Mudge;
Michael J. Geiger;
-
"A Partitioned Translation Lookaside Buffer Approach to Reducing Address Bandwidth"
2005 ▪
G. Tyson;
Matthew Farrens;
Arvin Park;
R. Fanfelle;
None Pius Ng;
-
"Misc: A Multiple Instruction Stream Computer"
2005 ▪
-
"Improving Program Efficiency by Packing Instructions into Registers"
2005 ▪
-
"An Energy Efficient Instruction Set Synthesis Framework for Low Power Embedded System Designs"
2005 ▪
IEEE Transactions on Computers
-
"Drowsy region-based caches"
2005 ▪
-
"Improving Program Efficiency by Packing Instructions into Registers"
2005 ▪
ACM SIGARCH Computer Architecture News
-
"Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation"
2005 ▪
Lecture notes in computer science
-
"PowerFITS: Reduce Dynamic and Static I-Cache Power Using Application Specific Instruction Set Synthesis"
2005 ▪
-
"FITS"
2004 ▪
-
"A prefetch taxonomy"
2004 ▪
IEEE Transactions on Computers
-
"Memory System Technologies for Future High-End Computing Systems"
2003 ▪
G. Tyson;
Sally A. McKee;
B R de Supinski;
F Mueller;
-
"A study of single-chip processor/cache organizations for large numbers of transistors"
2002 ▪
-
"Evaluating the performance of active cache management schemes"
2002 ▪
E. Davidson;
G. Tyson;
Jude A. Rivers;
Edward S. Tam;
V. Srinivasan;
-
"mlcache: a flexible multi-lateral cache simulator"
2002 ▪
E. Davidson;
G. Tyson;
Jude A. Rivers;
Edward S. Tam;
-
"Improving the accuracy and performance of memory communication through renaming"
2002 ▪
-
"On high-bandwidth data cache design for multi-issue processors"
2002 ▪
E. Davidson;
G. Tyson;
Todd M. Austin;
Jude A. Rivers;
-
"Allocation by conflict: a simple, effective multilateral cache management scheme"
2002 ▪
E. Davidson;
G. Tyson;
Edward S. Tam;
Stevan Vlaovic;
-
"Branch history guided instruction prefetching"
2002 ▪
E. Davidson;
G. Tyson;
V. Srinivasan;
M.J. Charney;
T.R. Puzak;
-
"Stack value file: custom microarchitecture for the stack"
2002 ▪
G. Tyson;
H.H.-S. Lee;
M. Smelyanskiy;
C.J. Newburn;
-
"Eager writeback-a technique for improving bandwidth utilization"
2002 ▪
G. Tyson;
Matthew Farrens;
Hsien-Hsin S. Lee;
-
"Instruction overhead and data locality effects in superscalar processors"
2002 ▪
-
"Quantifying instruction-level parallelism limits on an EPIC architecture"
2002 ▪
G. Tyson;
Hsien-Hsin S. Lee;
None Youfeng Wu;
-
"Evaluating the use of register queues in software pipelined loops"
2001 ▪
IEEE Transactions on Computers
-
"Evaluating the use of register queues in software pipelined loops"
2001 ▪
IEEE Transactions on Computers
-
"Hardware solutions to reduce effective memory access time."
2001 ▪
Deep Blue (University of Michigan)
E. Davidson;
G. Tyson;
Vijayalakshmi Srinivasan;
-
"Improving Bandwidth Utilization using Eager Writeback"
2001 ▪
?The ?journal of instruction-level parallelism
G. Tyson;
Matthew Farrens;
Hsien-Hsin S. Lee;
-
"Improving energy and performance of data cache architectures by exploiting memory reference characteristics."
2001 ▪
Deep Blue (University of Michigan)
-
"Eager writeback - a technique for improving bandwidth utilization"
2000 ▪
G. Tyson;
Matthew Farrens;
Hsien-Hsin S. Lee;
-
"Improving BTB performance in the presence of DLLs"
2000 ▪
-
"Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining"
2000 ▪
International Conference on Parallel Architectures and Compilation Techniques
-
"Region-based caching"
2000 ▪
-
"Classifying load and store instructions for memory renaming"
1999 ▪
G. Tyson;
Todd M. Austin;
Glenn Reinman;
Brad Calder;
Dean Tullsen;
-
"A high level simulator integrated with the Mirv compiler"
1999 ▪
ACM SIGARCH Computer Architecture News
G. Tyson;
Trevor N. Mudge;
Krisztián Flautner;
-
"The limits of instruction level parallelism in SPEC95 applications"
1999 ▪
ACM SIGARCH Computer Architecture News
G. Tyson;
Matthew A. Postiff;
David A. Greene;
Trevor N. Mudge;
-
"Active management of data caches by exploiting reuse information"
1999 ▪
IEEE Transactions on Computers
E. Davidson;
G. Tyson;
Jude A. Rivers;
Edward S. Tam;
V. Srinivasan;
-
"Allocation By Conflict: A Simple, Effective Cache Management Scheme"
1999 ▪
-
"Improving cache performance via active management."
1999 ▪
Deep Blue (University of Michigan)
-
"Performance Limits of Trace Caches"
1999 ▪
?The ?journal of instruction-level parallelism
-
"Untitled"
1999 ▪
International Journal of Parallel Programming
-
"Analyzing the working set characteristics of branch execution"
1998 ▪
International Symposium on Microarchitecture
-
"Utilizing reuse information in data cache management"
1998 ▪
E. Davidson;
G. Tyson;
Jude A. Rivers;
Edward S. Tam;
Matt Farrens;
-
"Computer architecture instruction at the University of Michigan"
1998 ▪
-
"Performance aspects of high-bandwidth multi-lateral cache organizations"
1998 ▪
-
"Improving the accuracy and performance of memory communication through renaming"
1997 ▪
-
"On high-bandwidth data cache design for multi-issue processors"
1997 ▪
International Symposium on Microarchitecture
E. Davidson;
G. Tyson;
Todd M. Austin;
Jude A. Rivers;
-
"Managing data caches using selective cache line replacement"
1997 ▪
International Journal of Parallel Programming
G. Tyson;
Matthew Farrens;
John Matthews;
Andrew R. Pleszkun;
-
"Evaluating the Effects of Predicated Execution on Branch Prediction"
1996 ▪
International Journal of Parallel Programming
-
"A modified approach to data cache management"
1995 ▪
International Symposium on Microarchitecture
G. Tyson;
Matthew Farrens;
John Matthews;
Andrew R. Pleszkun;
-
"A modified approach to data cache management"
1995 ▪
G. Tyson;
Matthew Farrens;
John Matthews;
Andrew R. Pleszkun;
-
"Code scheduling for multiple instruction stream architectures"
1994 ▪
International Journal of Parallel Programming
-
"A study of single-chip processor/cache organizations for large numbers of transistors"
1994 ▪
ACM SIGARCH Computer Architecture News
G. Tyson;
Matthew Farrens;
Andrew R. Pleszkun;
-
"A study of single-chip processor/cache organizations for large numbers of transistors"
1994 ▪
International Symposium on Computer Architecture
G. Tyson;
Matthew Farrens;
Andrew R. Pleszkun;
-
"The effects of predicated execution on branch prediction"
1994 ▪
-
"Techniques for extracting instruction level parallelism on MIMD architectures"
1993 ▪
International Symposium on Microarchitecture
-
"Techniques for extracting instruction level parallelism on MIMD architectures"
1993 ▪
-
"MISC"
1992 ▪
ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter
G. Tyson;
Matthew Farrens;
Andrew R. Pleszkun;
-
"Modifying VM hardware to reduce address pin requirements"
1992 ▪
ACM SIGMICRO newsletter/SIGMICRO newsletter/SIGMICRO, TCMICRO newsletter
-
"A partitioned translation lookaside buffer approach to reducing address bandwith (abstract)"
1992 ▪
ACM SIGARCH Computer Architecture News
G. Tyson;
Matthew Farrens;
Arvin Park;
R. Fanfelle;
None Pius Ng;
-
"A partitioned translation lookaside buffer approach to reducing address bandwith (abstract)"
1992 ▪
G. Tyson;
Matthew Farrens;
Arvin Park;
R. Fanfelle;
None Pius Ng;