Improving application efficiency by decoupling address generation and data access (DAGDA) featuring prepare to access memory (PAM) instruction, address generation structure (AGS). Associate DTLB access and L 1 DC tag check with address generation in a PAM instruction that reduces energy usage by avoiding many accesses to the DTLB and L 1 DC tag arrays and improves performance by obtaining loaded data earlier in the pipeline by prefetching data.
