Competitive Advantages:
Scalable, Mitigate llimit cycle oscillations, Lower area overhead, Reduces aging induced degradations.
A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.USF inventors have developed a reduced clock pulse width digital low-dropout regulator. Instead of using a conventional square wave as clock signal, a clock signal with reduced pulse width is utilized. With this design, the number of regulators utilized in the system and the size of each local regulator are scalable to satisfy the needs of different applications. It is demonstrated through simulation of an IBM POWER8 like processor that the proposed aging-aware design can achieve up to, respectively, 43.2% and 3X transient and steady state performance improvement. Additionally, more than 10% area overhead saving can be achieved over a five-year period.
Brochure
