The need for energy efficiency continues to grow for many classes of processors, including those for which performance remains vital. Not only is the data cache crucial for good performance, but it also represents a significant portion of the processor’s energy expenditure. We describe the implementation and use of a tagless access buffer (TAB) that greatly improves data access energy efficiency while slightly improving performance
The compiler recognizes memory reference patterns within loops and allocates these references to a small TAB. This combined hardware/software approach reduces energy usage by
(1) re- placing many first-level data cache (L1D) accesses with accesses to the smaller, more power-efficient TAB;
(2) removing the need to perform tag checks or data translation lookaside buffer (DTLB) lookups for TAB accesses; and
(3) minimizing DTLB lookups when transferring data between the L1D and the TAB.
Accesses to the TAB occur earlier in the pipeline, and data lines are automatically prefetched from lower memory levels, which result in a small performance improvement. In addition, we can avoid many unnecessary block transfers between other memory hierarchy levels by characterizing how data in the TAB is used.
With a combined size equal to that of a conventional 32-entry register file, a four-entry TAB eliminates 40% of L1D accesses and 42% of DTLB accesses, on average. This configuration reduces data-access related energy by 35% while simultaneously decreasing execution time by 3%.
