Research Terms
Computer Systems Computer Engineering
Industries
Software & Computer Systems Design
ACM, Member; 2004 - 2011
IEEE, Member; 2000 - 2011
This test pattern generator improves detection of side-channel signatures caused by hardware Trojans to reveal potential attacks to System-on-Chip (SoC) devices. Detecting hardware Trojans is critical to ensuring the security and trustworthiness of SoC designs. Side-channel analysis is a common tool for detecting Trojans that analyzes various side-channel signatures such as power and current delay. Deviations in these signatures can identify malicious circuitry modifications. Generating the right circuitry test patterns that expose these modifications is a major challenge. For large SoC designs, test generation time grows exponentially with the design complexity, and Trojan-caused side-channel signatures are marginal compared to noise and process variations.
Researchers at the University of Florida have developed an efficient procedure to generate test patterns that maximize the sensitivity of side-channel analysis to Trojan signatures.
Reliable hardware Trojan detection using side-channel analysis to ensure secure SoCs
This test generation mechanism facilitates the exposure of malicious hardware and intellectual property (IP) modifications via side-channel analysis using dynamic current. The design formalizes test pattern generation as a searching problem and solves the optimization using a genetic algorithm. The process quickly finds the test patterns that best maximize switching in the suspicious circuitry regions while minimizing switching in the rest of the circuit. These tests dramatically improve the side-channel sensitivity during side-channel analysis, enabling it to identify Trojans in SoCs to avoid malicious IP attacks.
This malicious hardware detection system identifies hardware Trojans present in system-on-chips that can lead to undesired information leakage and system malfunction. System-on-chips are critical components of nearly all modern electrical systems, and the system-on-chip market should reach $205 billion globally by 2023. Insuring the integrity of system-on-chips is a crucial step in quality and security assurance of larger electronics. Current methods for detecting Hardware Trojans in system-on-chips can be time-consuming and are limited due to the high computational complexity of the methods, inability to detect stealthy Trojans, and inability to distinguish Hardware Trojan activity from background activity.
Researchers at the University of Florida have designed a malicious hardware detection system that is more effective at detecting Hardware Trojans and less time-consuming than available detection methods. This system promotes system-on-chip security and mitigates unwanted information leakage and larger system malfunction.
Detects malicious Hardware Trojans in system-on-chips more accurately and more quickly than available Hardware Trojan detection systems.
This system detects malicious Hardware Trojans in system-on-chips to prevent information leakage and wider system failure. This system detects Hardware Trojans more accurately than other detection systems by using critical path analysis to increase side-channel sensitivity and better distinguish Hardware Trojan activity from background activity. This system also detects Hardware Trojans more quickly than other systems by applying reinforcement learning to rapidly and autonomously generate tests that detect Hardware Trojans using delay-based analysis.
This routing protocol calculates the trustworthiness of IP cores in network-on-chip (NoC) systems and makes routing decisions to avoid malicious cores that corrupt transmissions and hamper performance. Many system-on-chip (SoC) designs communicate via a network connecting various system cores, many of which are manufactured by multiple third-party vendors to lower cost and production time. Some untrusted vendors produce malicious cores that tamper with packet transmissions and cause multiple retransmissions and stall cycles. Efforts to limit malicious corruption of packets rely on authentication schemes, but these schemes introduce unacceptable overhead on resource constrained network-on-chip systems.
Researchers at the University of Florida have developed a trust-aware routing protocol that effectively avoids malicious IPs on a microchip. By communicating only through trusted cores, a network-on-chip system avoids transmission corruption and delay, uses less energy, and shortens encryption time.
Routing protocol to avoid malicious IPs in network-on-chip based system-on-chips
The routing protocol calculates trust relationships on a spectrum between pairs of nodes, which represent potentially-malicious IP cores in an SoC. The protocol expands and updates the nodal relationships continuously to determine the trust value of nodal paths in order to send transmissions only from secure zone to secure zone. If a malicious node corrupts a transmission, the retransmission reduces that node’s trust value and an algorithm determines an alternative path. SoCs suffer significant packet transfer delays in the presence of malicious IPs. Data from both real and synthetic benchmarks demonstrate that this protocol reduces packet transmission delays and energy consumption nearly to the level of a perfectly secure network-on-chip.
